The present invention is directed to integrated circuit design verification, and more particularly to a system, method, and apparatus for analyzing post layout timing violations.
Simulation programs are frequently used for testing integrated circuits. Integrated circuit production is characterized by high initial costs for the production of the first “copy” followed by low marginal costs for each successive copy. Testing of a design for an integrated circuit prior to production is almost imperative.
The design timing verification starts with the delivery of a design layout of the integrated circuit. A design layout is a functional and timing representation of the design of an integrated circuit. The design layout starts from an implementation description of the functionality that is synthesized from a behavioral language description. During design verification, a design layout is tested for operational errors. The operational errors are then used to diagnose any errors in the design layout and modify the design layout. The modified design layout is then retested. The testing and debugging cycle continue until a design layout is developed which meets the design verification requirements. The final design layout is then used for production of integrated circuits.
The design layouts are tested by simulating the operation of the design layouts. The operation of the design layouts is simulated by what are known as simulation tools. One of the most popular simulation tools is known as the Verilog™ simulator. The Verilog™ simulator performs a variety of simulations which test various aspects of the integrated circuit, including timing simulations.
Timing simulations are used to test the synchronization of the design layout. One area of testing tests the arrival of signals at flip-flops. In an integrated circuit, latches are characterized by a clocked input which is controlled by a clock. The clock generates a clock signal with a brief pulse at predetermined time intervals. The input signals must arrive prior to the clock signal. If the signal arrives after the clock signal, the latch will not recognize the input. To avoid the foregoing problem, a design layout is simulated. When an input signal does not arrive at the expected time during the simulation, a timing violation occurs. The foregoing simulation is known as a post-layout gate level back annotated simulation.
The timing violations during a post-layout gate level back annotated simulation are reported in a log file. The log file includes records which indicate various information related to each timing violation, such as the time, location, and type of timing violation. The log file can then be analyzed by a verification engineer to modify the design layout.
Analysis of the log file is very time consuming. There are usually an extremely high number of timing violations reported in the log file. Many of the high number of timing violations are either not useful for diagnostic purposes or redundantly indicate a problem. Additionally, the timing violations are not sorted in a manner that is useful for debugging. As a result, analysis of the timing violations is done on a brute force violation-by-violation basis. Due to the lack of organization of the timing violations, overall trends are hard to identify from individual timing violations, because the individual timing violations are sparsely located throughout the log file.
Accordingly, it would be advantageous if a tool for analyzing timing violations is provided. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments presented in the remainder of the present application with references to the drawings.